The present invention relates to electronic devices, and more particularly to semiconductor structures including memory devices, such as eDRAM devices, formed within a silicon-on-insulator (SOI) substrate.
Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size affects chip density, and cost, reducing cell area is one of the DRAM designer's primary goals.
One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Trench capacitors can be formed by etching deep trenches in a silicon wafer and forming vertically oriented capacitors within each deep trench. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge. Each deep trench may have a depth on the order of 1 μm or greater.
Trench-type memory devices are advantageous, in comparison to planar memory configurations, for increased density, performance and lithographic considerations. Trench-type memory devices increase density by reducing the cell area of each memory device, therefore allowing for closer positioning of adjacent memory devices.
There is interest in integrating the excellent drive current and density of memory devices with the superior logic devices that can be formed on silicon-on-insulator (SOI) substrates, to obtain high density memory embedded dynamic random access memory (eDRAM). SOI substrates reduce parasitic capacitance within the integrated circuit and reduce individual circuit loads, thereby improving circuit and chip performance.
With eDRAM on an SOI substrate, the buried oxide (BOX) is used as a collar oxide, simplifying the overall fabrication process. However, the collar oxide can be attacked easily during wet processing, especially during node dielectric material removal before strap deposition.
Radens et al. U.S. Pat. No. 6,426,252, the disclosure of which is incorporated by reference herein, discloses an SOI DRAM memory cell in which the BOX layer is intentionally etched to form the strap therein. There is no recognition of the need to avoid the undercutting of the BOX layer.
Adkisson et al. U.S. Pat. No. 6,590,259, the disclosure of which is incorporated by reference herein, discloses an SOI eDRAM structure wherein the BOX layer is not undercut. There is no recognition of the problem of BOX layer undercutting or the need to avoid the undercutting of the BOX layer.
Mandelman et al. U.S. Pat. No. 6,815,749, the disclosure of which is incorporated by reference herein, discloses that the BOX layer is purposely undercut to form a strap therein. The reference recognizes that the tolerances are such that there is no risk of shorting adjacent trenches through the BOX layer.
Ho et al. U.S. Patent Application Publication US 2008/0064178, the disclosure of which is incorporated by reference herein, discloses the addition of a sidewall spacer to protect the BOX layer prior to the formation of the deep trench. After the formation of the deep trench, the sidewall spacer is removed.
Accordingly, there is a need for an improvement in the design and manufacturing of semiconductor structures, such as eDRAM on SOI substrates, to protect the BOX layer during processing.